This invention relates to a semiconductor device having a MOS source follower circuit integrated on a semiconductor substrate.
FIG. 1 shows a MOS source follower circuit formed on a conventional semiconductor substrate. FIG. 2 illustrates the circuit diagram of the MOS source follower circuit which is shown in FIG. 1.
In FIG. 1 a p-well 102 is formed on a n-type semiconductor substrate 101 with a well known technique. On this single p-well, MOS transistors 103 and 104 are formed. The MOS transistor 103 is an enhancement-type driver transistor of the source follower circuit which has n.sup.+ areas 105 and 106 into which a high-density n-type impurity is diffused as a drain and a source, respectively, and also has a polycrystalline silicon electrode 107 as a gate electrode in structure. The MOS transistor 104 is a depletion-type load transistor of the source follower circuit which has n.sup.+ type areas 106 and 108 as a drain and a source, respectively, and also has a polycrystalline electrode 109 as a gate electrode in structure. Note here that in both transistors their gate oxide films are omitted in FIG. 1.
The drain 105 of the transistor 103 is connected to an electrode terminal V.sub.D with a wiring material such as aluminum, while the gate electrode 107 is connected to an input terminal V.sub.IN with the wiring material. The n.sup.+ area 106, which plays both the roles of the source of the transistor 103 and the drain of the transistor 104, is connected to an output terminal V.sub.OUT. The source 108 and the gate 109 of the transistor 104 are connected to a point of reference potential. The semiconductor substrate 101 is connected to a substrate bias terminal V.sub.sub, and to this substrate a prescribed bias voltage is applied. The p-well 102 is connected to the point of reference potential via p.sup.+ layers 110 and 111 which realize ohmic contact with the wiring material.